1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to a multi-bank semiconductor memory device having a plurality of banks. More specifically, the invention relates to a multi-bank DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a plurality of banks are provided for improving data access efficiency.
FIG. 25 is a schematic diagram showing an entire structure of a conventional multi-bank DRAM Referring to FIG. 25, DRAM 900 includes banks BK#A and BK#B. Bank BK#A includes a memory array 902a having memory cells (not shown) arranged in rows and columns and word lines WL (0)-WL (m) arranged corresponding to respective memory cell rows, a row decoder 903a generating a row decode signal for designating a row in memory array 902a, and a word line driver for driving, into the selected state, a word line arranged corresponding to an addressed row according to the row decode signal from row decoder 903a. Memory array 902a includes a global data bus GDB provided in a direction intersecting word lines WL (0)-WL (m). Global data bus GDB is coupled to an input/output buffer 906a. 
Bank BK#B similarly includes a memory array 902b having memory cells (not shown) arranged in rows and columns and word lines WL (0)-WL (m) provided corresponding to respective memory cell rows, a row decoder 903b for decoding a row address signal to generate a row decode signal for specifying an addressed row, and a word line driver 904b for driving, into the selected state, a word line arranged corresponding to an addressed row in memory array 902b according to the row decode signal from row decoder 903b. Memory array 902b also includes a global data bus GDB provided in the direction intersecting word lines WL (0)-WL (m). Global data bus GDB of memory array 902b is coupled to an input/output buffer 906b. 
Input/output buffers 906a and 906b are both coupled to N-bit IO lines IO (0)-IO (Nxe2x88x921) to input/output N-bit data. Respective IO lines coupled to input/output buffers 906a and 906b are interconnected by internal data transmission lines IL (0)-IL (Nxe2x88x921). These internal data transmission lines IL (0)-IL (Nxe2x88x921) are coupled to a load circuit 907 to be precharged to a predetermined voltage level.
Input/output buffers 906a and 906b are also coupled to a group of N-bit data input/output terminals 910.
A control circuit 905 is commonly provided to banks BK#A and BK#B. Control circuit 905 controls operations of banks BK#A and BK#B in accordance with an address signal (multi-bit address) ADD supplied to an address terminal 908 and a command CMD supplied to a command input terminal 909. Specifically, when a bank address included in address signal ADD designates bank BK#A, for example, control circuit 905 generates a control signal necessary for an operation designated by command CMD to supply the generated signal to bank BK#A. For example, if command CMD designates array activation (word line selection) and a bank address included in address signal ADD designates bank BK#A, control circuit 905 activates row decoder 903a and word line driver 904a provided for bank BK#A. Accordingly, in memory array 902a, a word line corresponding to a row designated by address signal ADD is driven into the selected state.
If data access (data writing or reading) for bank BK#A is designated by address signal ADD and command CMD, control circuit 905 generates a control signal for activating input/output buffer 906a of bank BK#A to allow data to be transferred (written/read) between corresponding data bus GDB and data input/output terminal group 910.
In the DRAM shown in FIG. 25, banks BK#A and BK#B are provided with respective row decoders for row selection and respective word drivers as well as respective input/output buffers for data input/output. If a row selecting circuit, a column selecting circuit (not shown) and the data input/output circuit are provided for each bank as is done in DRAM 900, a possible problem is that increase in number of banks results in increase in chip area or area penalty of DRAM 900.
In order to overcome such a problem of increase in chip area due to the structure having the row selection, column selection and data input/output circuits provided for each bank, a bank structure shown in FIG. 26 is employed in an embedded DRAM for example formed on the same semiconductor chip as that of logic.
FIG. 26 is a schematic diagram showing an entire structure of a conventional embedded DRAM. In FIG. 26, embedded DRAM 950 includes banks BK#0 and BK#1. Bank BK#0 includes memory sub arrays 952a and 952b aligned in a row direction and a row selection circuit 954a for selecting rows in respective memory sub arrays 952a and 952b. Row selection circuit 954a includes a row decoder and a word line driver.
Bank BK#1 includes memory sub arrays 952c and 952d aligned in the row direction, and a row selection circuit 954b provided between memory sub arrays 952c and 952d for selecting rows in respective memory sub arrays 952c and 952d. Row selection circuit 954b also includes a row decoder and a word line driver. Memory sub arrays 952a-952d each include (m/2)+1 word lines WL (0)-WL (m/2).
A global data bus GDB is commonly provided to memory sub arrays aligned in the column direction. Specifically, a global data bus GDB coupled to an input/output buffer 956a is commonly provided to memory sub arrays 952a and 952c and a global data bus GDB coupled to an input/output buffer 956b is commonly provided to memory sub arrays 952b and 952d. These global data buses GDBs each have a bit width of N/2.
Input output buffer 956a is coupled to a group of data input/output nodes 960a with a bit width of N/2 through internal data lines IO less than 0 greater than  to IO less than N/2xe2x88x921 greater than  and input/output buffer 956b is coupled to a group of data input/output nodes 960b with a bit width of N/2 through internal data lines IO less than N/2 greater than  to IO less than Nxe2x88x921 greater than .
A control circuit 958 is provided commonly to banks BK#0 and BK#1 for controlling operations of these banks BK#0 and BK#1. Control circuit 958 receives an address signal ADD supplied to an address input node 962 and a command CMD supplied to a command input node 964 to generate a control signal necessary for an operation designated by this command signal CMD.
In the structure of the embedded DRAM shown in FIG. 26, input/output buffers 956a and 956b are shared by banks BK#0 and BK#1 Global data bus GDB is also shared by banks BK#0 and BK#1 Global data bus GDB has a bit width of N/2. Arrangement of banks BK#0 and BK#1 aligned in the column direction makes it possible to arrange the input/output buffers and global data buses commonly to these banks to reduce the chip area of the embedded DRAM.
In the bank structure as shown in FIG. 26, a word line must be selected in each of the two memory sub arrays aligned in the row direction. Compared with the bank structure shown in FIG. 25, the equivalent total length of a word line is made longer and a greater number of sense amplifiers are simultaneously activated. Resultant problems are increase in current consumption in row selection and increase in load of a boosted voltage source circuit generating a boosted voltage used for a word line drive signal transmitted to a selected word line.
It would be possible to reduce the power consumption of the embedded DRAM as shown in FIG. 26 by activating only one memory sub array in a selected bank.
Specifically, as shown in FIG. 27, input/output buffers 956a and 956b are coupled commonly to a group of data input/output nodes 966 through the internal data bus lines IO less than Nxe2x88x921;0 greater than . One of memory sub arrays 952a and 952b or one of memory sub arrays 952c and 952c is specified by address signal bits. According to such a structure, only one memory sub array is activated in a selected bank so that current consumption in row selection can be reduced, compared with the current consumed in the bank structure shown in FIG. 26.
However, in the structure of embedded DRAM 950 oriented to reduction of current consumption as shown in FIG. 27, if the number of data input/output bits is the same N-bit, n-bit memory cells must be selected in one memory sub array and accordingly global data bus GDB must have the bit width of N bits. If the memory sub arrays have the same number of columns, the page length of columns in one memory sub array (the number of column addresses included in one page) decreases by half.
Therefore, the embedded DRAMs shown in FIGS. 26 and 27 need individual optimal designs according to respective specifications, and there is thus no compatibility between the embedded DRAMs shown in FIGS. 26 and 27.
A problem of low design efficiency then arises due to the need of optimal design of a DRAM according to its specification as well as design change for each DRAM according to specification change.
An object of the present invention is to provide a semiconductor memory device that flexibly accommodates a change in specification.
Another object of the invention is to provide a DRAM that can be adapted for any of different page sizes.
A semiconductor memory device according to the invention includes a plurality of banks each divided into a plurality of memory blocks and activated independently of each other, and a control circuit provided commonly to these banks for controlling access to the banks. According to a mode instruction signal, the control circuit allows access to the banks on the basis of a memory block in a first mode and allows access on the basis of a bank in a second mode.
The mode instruction signal is used for changing the manner in which the bank is accessed, i.e., whether the access is made on the basis of a memory block or a bank. In a low power consumption mode, access is made on the basis of a memory block. In order to increase the page size, access is made on the basis of a bank. In this way, the internal bank structure can easily be changed according to application of the semiconductor memory device. In addition, only the mode instruction signal is used for changing the operation manner and changing the manner in which internal data lines are connected. The semiconductor memory device can thus easily operate in a plurality of operation modes with the same chip layout.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.